Use only the SV test APIs supplied with the developer's kit to stimulate your CLĭesign.
The scripts/ directory is where you must launch all simulations. Once your test is written, you are ready to run a simulation. Tb.poke_ocl(`CNTL_REG, 32'h0003) // start read & write Tb.poke_ocl(`RD_ADDR_HIGH, pcim_address) // read address high Tb.poke_ocl(`RD_ADDR_LOW, pcim_address) // read address low Tb.poke_ocl(`RD_INSTR_INDEX, 0) // read index Tb.poke_ocl(`WR_ADDR_HIGH, pcim_address) // write address high Tb.poke_ocl(`WR_ADDR_LOW, pcim_address) // write address low Tb.poke_ocl(`WR_INSTR_INDEX, 0) // write index
#Fpga simulation memory install#
Install the HDK and setup environmentĪWS FPGA HDK can be cloned and installed on your EC2 instance or server by calling:
#Fpga simulation memory license#
Please refer to the release notes or the supported Vivado version for the exact version of Vivado tools, and the required license components. One easy way is to have a pre-installed environment is to use the AWS FPGA Developer AMI available on AWS Marketplace which comes with pre-installed Vivado tools and license.įor developers who like to work on-premises or different AMI in the cloud, AWS recommends following the required license for on-premise document. Quick Start Have an EC2 instance or other server with Xilinx Vivado tools and an active license.
#Fpga simulation memory code#
If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1. SimulatorĬadence Incisive Enterprise Simulator(IES)ĭevelopers can write their tests in SystemVerilog and/or C languages. See table below for supported simulator versions. AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM, MentorGraphics' Questa, Cadence Incisive and Synopsys' VCS RTL simulators. RTL Simulation for Verilog/VHDL Custom Logic Design with AWS HDK Introductionĭevelopers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI).
0 kommentar(er)
